PD6710 Datasheet, PDF (109/138 Pages) Intel Corporation – ISA-to-PC-Card (PCMCIA) Controllers

ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 30. Input Clock Specification (Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
T_CLKP
Input clock period,
internal clock
69.84 – 0.1%
69.84 + 0.1%
T_CLKP
Input clock period,
external clock
V_IHmin
V_ILmax
V_IHCmin
V_ILCmax
CLK input high voltage
CLK input low voltage
CLK input high voltage
CLK input low voltage
40 – 0.1%
2.0
0.7 V_DD
Figure 22. Input Clock Specification
t₁
t₂
V_IHmin, V_IHCmin
40 + 0.1%
0.8
0.2 V_DD
Units
ns
ns
V
V
V
V
Conditions
Normal synthesizer
operation. Misc Control 2
register, bit 0 = ‘0’. CLK
pin at 14.318 MHz.
Synthesizer bypassed.
Misc Control 2 register,
bit 0 = ‘1’.
CLK pin at 25 MHz.
CORE_VDD = 3.0 V
CORE_VDD = 3.6 V
CORE_VDD = 4.5 V
CORE_VDD = 5.5 V
V_center
V_ILmax, V_ILCmax
CLK
t₃
t₄
T_CLKP
16.4.5
PC Card Bus Timing Calculations
Calculations for minimum PC Card cycle Setup, Command, and Recovery timings are made by
first calculating factors derived from the applicable timer set’s timing registers and then by
applying the factor to an equation relating it to the internal clock period.
The PC Card cycle timing factors, in terms of the number of internal clocks, are calculated as
follows:
S = (N_pres × N_val) + 1
C = (N_pres × N_val) + 1
R = (N_pres × N_val) + 1
Datasheet
109