82551IT Datasheet, PDF (89/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

Networking Silicon — 82551IT
Table 57. Measure and Test Condition Parameters
V_test
V_step (rising edge)
0.4V_CC
0.285V_CC
V_step (falling edge)
V_max
Input Signal Edge
Rate
0.615V_CC
0.4V_CC
1
V
V Min Delay
V Max Delay
V Min Delay
V Max Delay
V
V/ns
NOTE: Input test is done with 0.1V_CC overdrive. V_max specifies the maximum peak-to-peak waveform allowed
for testing input timing.
11.4.2.2 PCI Timings
Table 58. PCI Timing Parameters
Symbol
Parameter
Min
T14 t_val
T15 t_val(ptp)
T16 t_on
T17 t_off
T18 t_su
T19 t_su(ptp)
T20 t_h
T21 t_rst
T22 T_rst-clk
T23 T_rst-off
PCI CLK to Signal Valid Delay
2
PCI CLK to Signal Valid Delay (point-
to-point)
2
Float to Active Delay
2
Active to Float Delay
Input Setup Time to CLK
7
PCI Input Setup Time to CLK (point-to-
point)
10
Input Hold Time from CLK
0
Reset Active Time After Power Stable
1
PCI Reset Active Time After CLK
Stable
100
Reset Active to Output Float Delay
Max Units
11
ns
12
ns
ns
28
ns
ns
ns
ns
ms
clocks
40
ns
Notes
1, 2, 3
1, 2, 3
1
1
3, 4
3, 4
5
5
5
5, 6
NOTES:
1. Timing measurement conditions are illustrated in Figure 21.
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
4.2.3.2.
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times
and input setup times than bussed signals. All other signals are bussed.
4. Timing measurement conditions are illustrated in Figure 22.
5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
6. All PCI interface output drivers are floated when RST# is active.
11.4.2.3
Flash Interface Timings
The 82551IT is designed to support up to 150 ns of Flash access time. The V_PP signal in the Flash
implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled
only by the FLWE# pin.
Table 59 provides the timing parameters for the Flash interface signals. The timing parameters are
illustrated in Figure 23 and Figure 24.
Datasheet
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