82551IT Datasheet, PDF (38/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

82551IT — Networking Silicon
5.5.1
EEPROM Address Map
Table 12 lists the EEPROM address map for the 82551IT Fast Ethernet Controller.
Table 12. 82551IT EEPROM Address Map
Word
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh:0Fh
10h:22h
23h
24h:2Fh
30h:33h
34h:3Eh
3Fh
40h:FEh
FFh
High Byte (Bits 15:8)
Low Byte (Bits 7:0)
Ethernet Individual Address Byte 2
Ethernet Individual Address Byte 1
Ethernet Individual Address Byte 4
Ethernet Individual Address Byte 3
Ethernet Individual Address Byte 6
Ethernet Individual Address Byte 5
Compatibility Byte 1
Compatibility Byte 0
Reserved
Controller Type
Connectors
Primary PHY Record, high byte
Primary PHY Record, low byte
Secondary PHY Record, high byte
Secondary PHY Record, low byte
PWA Byte 1
PWA Byte 2
PWA Byte 3
PWA Byte 4
EEPROM_ID, high byte
EEPROM_ID, low byte
Subsystem_ID, high byte
Subsystem_ID, low byte
Subsystem_Vendor, high byte
Subsystem_Vendor, low byte
Reserved
Reserved
Device ID, high byte
Device ID, low byte
Reserved
Reserved
Reserved
64-word EEPROM Checksum, high byte
64-word EEPROM Checksum, low byte
Reserved
256-word EEPROM Checksum, high byte 256-word EEPROM Checksum, low byte
Note: Refer to the 82551QM/ER/IT EEPROM Map and Programming Information for more details.
5.6
10/100 Mbps CSMA/CD Unit
The 82551IT CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u
Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions such as
transmission, reception, collision handling, etc. The 82551IT CSMA/CD unit communicates with
the internal PHY unit through a standard Media Independent Interface (MII), as specified by IEEE
802.3, Chapter 22. This is a 10/100 Mbps mode in which the data stream is nibble-wide and the
serial clocks run at either 25 or 2.5 MHz.
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Datasheet