82551IT Datasheet, PDF (11/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

Networking Silicon — 82551IT
3.0
Performance Enhancements
All of Intel’s Fast Ethernet controllers have the ability to support full wire speeds. The 82551IT has
been designed to provide improved networking throughput. Performance is limited to the system’s
ability to feed data to the network controller.
As networks grow, the task of servicing the network becomes a large burden on the platform.
System bottlenecks prevent optimal performance in typical operating conditions. Thus, to help
alleviate these issues, Network Operating System (NOS) vendors are establishing normalized off-
load specifications. These specifications define the types of off-load support required by the OS
and interface between the network drivers. The 82551IT provides support for these initiatives and
enables an improvement in platform network efficiency. With the pervasiveness of Internet
Protocols, the off-load capabilities have focused on improving IP efficiency. As part of this effort,
the 82551IT includes support for Multiple Priority Transmit Queues.
3.1
Multiple Priority Transmit Queues
The 82551IT supports two queues: High Priority Queue (HPQ) and Low Priority Queue (LPQ).
The 82551IT provides a method for the driver to modify the HPQ while processing data. A new
read only register is defined in the Control/Status Register (CSR) that enables the driver to change
the transmit priority of elements within the HPQ. When software reads this register, the address of
the next Command Block to be processed by the 82551IT on the HPQ is returned. After reading
this register, software can freely modify the next Command Block (for example, overwrite it with a
different Command Block) and any subsequent Command Block, without any conflict with the
82551IT.
Note: The 82551IT Windows* driver supports the Command Block Pointer register (in the CSR).
3.2
Early Release
Like the 82558, 82559 and 82550, the 82551IT supports a 3 KB transmit FIFO. The 82551IT
provides a transmit FIFO enhancement called “early release” that effectively increases the amount
of free capacity in the transmit FIFO. The enabling of early release is controlled through
configuration space and occurs when the following conditions are met:
1. The transmitted frame is the oldest one in the queue (in other words, it is located at the head of
the queue).
2. The transmitted frame has been completely transferred to the XMT-SRAM and processed (for
example, XSUM). Large frames (greater than 3 KB) are never candidates for an early release.
3. When the preemptive queue mechanism is on, a frame which satisfies condition 2 may not
satisfy condition 1 and therefore will not benefit from an early release.
4. More than 128 bytes have already been transferred to the XMT-SYNC-FIFO. This condition
guarantees that at least one slot time elapsed (collision window).
Datasheet
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