82551IT Datasheet, PDF (48/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

82551IT — Networking Silicon
7.1.2
PCI Command Register
The 82551IT Command register at word address 04h in the PCI configuration space provides
control over the 82551IT’s ability to generate and respond to PCI cycles. If a 0 is written to this
register, the 82551IT is logically disconnected from the PCI bus for all accesses except
configuration accesses. The format of this register is shown in the figure below.
Figure 14. PCI Command Register
15
10 9 8 7 6 5 4 3 2 1 0
Reserved
0000
SERR# Enable
Parity Error Response
Memory Write and Invalidate Enable
Bus Master Enable
Memory Space
I/O Space
Bits three, five, seven, and nine are set to 0b. Table 13 describes the bits of the PCI Command
register.
Table 13. PCI Command Register Bits
Bits
15:10
Name
Reserved
8
SERR# Enable
6
Parity Error Control
4
Memory Write and
Invalidate Enable
2
Bus Master
1
Memory Space
0
I/O Space
Description
These bits are reserved and should be set to 0b.
This bit controls a device’s ability to enable the SERR# driver. A value of 0b
disables the SERR# driver. A value of 1b enables the SERR# driver. This
bit must be set to report address parity errors. In the 82551IT, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to parity errors. A value of 0b causes
the device to ignore any parity errors that it detects and continue normal
operation. A value of 1b causes the device to take normal action when a
parity error is detected. This bit must be set to 0b after RST# is asserted. In
the 82551IT, this bit is configurable and has a default value of 0b.
This bit controls a device’s ability to use the Memory Write and Invalidate
command. A value of 0b disables the device from using the Memory Write
and Invalidate Enable command. A value of 1b enables the device to use
the Memory Write and Invalidate command. In the 82551IT, this bit is
configurable and has a default value of 0b.
This bit controls a device’s ability to act as a master on the PCI bus. A
value of 0b disables the device from generating PCI accesses. A value of
1b allows the device to behave as a bus master. In the 82551IT, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to the memory space accesses. A
value of 0b disables the device response. A value of 1b allows the device
to respond to memory space accesses. In the 82551IT, this bit is
configurable and its default value of 0b.
This bit controls a device’s response to the I/O space accesses. A value of
0b disables the device response. A value of 1b allows the device to
respond to I/O space accesses. In the 82551IT, this bit is configurable and
the default value of 0b.
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Datasheet