82551IT Datasheet, PDF (52/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

82551IT — Networking Silicon
7.1.9
PCI Base Address Registers
One of the most important functions for enabling superior configurability and ease of use is the
ability to relocate PCI devices in address spaces. The 82551IT contains three types of Base
Address Registers (BARs). Two are used for memory mapped resources, and one is used for I/O
mapping. Each register is 32 bits wide. The least significant bit in the BAR determines whether it
represents a memory or I/O space. The figures below show the layout of a BAR for both memory
and I/O mapping. After determining this information, power-up software can map the memory and
I/O controllers into available locations and proceed with system boot. In order to do this mapping
in a device independent manner, the base registers for this mapping are placed in the predefined
header portion of configuration space. Device drivers can then access this configuration space to
determine the mapping of a particular device.
Figure 17. Base Address Register for Memory Mapping
31
Prefetchable
Base Address
43210
0
Type:
00 - locate anywhere in 32-bit address space
01 - locate below 1 MB
10 - locate anywhere in 64-bit address space
11 - reserved
Memory space indicator
Figure 18. Base Address Register for I/O Mapping
31
Base Address
Reserved
I/O space indicator
210
01
Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory
or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that
map to I/O space must return 1b in bit 0.
Base registers that map into I/O space are always 32 bits wide with bit 0 hard-wired to a 1b, bit 1 is
reserved and must return 0b on reads, and the other bits are used to map the device into I/O space.
The number of upper bits that a device actually implements depends on how much of the address
space the device will respond to. For example, a device that wants a 1 MB memory address space
would set the most significant 12 bits of the base address register to be configurable, setting the
other bits to 0b.
The 82551IT contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM.
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Datasheet