82551IT Datasheet, PDF (67/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

Networking Silicon — 82551IT
9.0
PHY Unit Registers
The 82551IT provides status and accepts management information via the Management Data
Interface (MDI) within the CSR space.
Acronyms mentioned in the registers are defined as follows:
SC -
self cleared
RO - read only
E-
EEPROM setting affects content
LL -
latch low
LH - latch high
9.1
MDI Registers 0 - 7
9.1.1
Register 0: Control Register
Table 24. Register 0: Control
Bit(s)
Name
15
Reset
14
Loopback
13
Speed Selection
12
Auto-Negotiation
Enable
Description
Default R/W
This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns
a value of one until the reset process has completed and
accepts a read or write transaction.
1 = PHY Reset
This bit enables loopback of transmit data nibbles from
the TXD[3:0] signals to the receive data path. The PHY
unit’s receive circuitry is isolated from the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of “dead
time.”
Note also that the loopback configuration bit takes priority
over the Loopback MDI bit.
1 = Loopback enabled
0 = Loopback disabled (Normal operation)
This bit controls speed when Auto-Negotiation is disabled
and is valid on read when Auto-Negotiation is disabled.
1 = 100 Mbps
0 = 10 Mbps
This bit enables Auto-Negotiation. Bits 13 and 8, Speed
Selection and Duplex Mode, respectively, are ignored
when Auto-Negotiation is enabled.
1 = Auto-Negotiation enabled
0 = Auto-Negotiation disabled
0
RW
SC
0
RW
1
RW
1
RW
Datasheet
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