82551IT Datasheet, PDF (49/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

Networking Silicon — 82551IT
7.1.3
PCI Status Register
The 82551IT Status register is used to record status information for PCI bus related events. The
format of this register is shown in the figure below.
Figure 15. PCI Status Register
31 30 29 28 27 26 25 24 23 22 21 20 19
16
0 0 01 1 0 0 1 Reserved
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
Devsel Timing
Parity Error Detected
Fast Back To Back (target)
Capabilities List
Note: Bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. The PCI Status register bits
are described in Table 14.
Table 14. PCI Status Register Bits
Bits
Name
Description
31
30
29
28
27
26:25
Detected Parity Error
This bit indicates whether a parity error is detected. This bit must be set by
the device when it detects a parity error, even if parity error handling is
disabled (as controlled by the Parity Error Response bit in the PCI
Command register, bit 6). In the 82551IT, the initial value of the Detected
Parity Error bit is 0b. This bit is set until cleared by writing a 1b.
This bit indicates when the device has asserted SERR#. In the 82551IT,
Signaled System Error the initial value of the Signaled System Error bit is 0b. This bit is set until
cleared by writing a 1b.
Received Master
Abort
This bit indicates whether or not a master abort has occurred. This bit must
be set by the master device when its transaction is terminated with a
master abort. In the 82551IT, the initial value of the Received Master Abort
bit is 0b. This bit is set until cleared by writing a 1b.
Received Target Abort
This bit indicates that the master has received the target abort. This bit
must be set by the master device when its transaction is terminated by a
target abort. In the 82551IT, the initial value of the Received Target Abort
bit is 0b. This bit is set until cleared by writing a 1b.
This bit indicates whether a transaction was terminated by a target abort.
Signaled Target Abort This bit must be set by the target device when it terminates a transaction
with target abort. In the 82551IT, this bit is always set to 0b.
DEVSEL# Timing
These two bits indicate the timing of DEVSEL#:
00b - Fast
01b - Medium
10b - Slow
11b - Reserved
In the 82551IT, these bits are always set to 1b, medium.
Datasheet
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