82551IT Datasheet, PDF (102/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

82551IT — Networking Silicon
AD[31:0]
C/BE[3:0]
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
PCI_5V
2) The voltage on VIO determines the slope of the signals on the bus. Although the device
communicates if VIO is connected to 3.3V in 3.3V PCI systems, optimal performance is
acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage.
2
1
0.1uF
100 K ohm
1) The decoupling
capacitor should be
added to the VIO pin.
All Vcc pins are connected together on the PCB
level. The power on the symbol is broken down
between core power (Vcc), local bus power (Vccpl),
transmit power (Vcct), and PCI power (Vccpp) just
for clarity.
G2 _VIO
82551IT
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0
C/BE1
C/BE2
C/BE3
INTA
PERR#
SERR#
IDSEL
REQ#
GNT#
RST#
CLK
ISOLATE#
AUX_GOOD
PME#
CLKRUN#
62 K ohm
N7
M7
P6
P5
N5
M5
P4
N4
P3
N3
N2
M1
M2
M3
L1
L2
K1
E3
D1
D2
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
A8
B8
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
FLA16
FLA15/EESK
FLA14/EEDO
FLA13/EEDI
FL A12
FLA11
FLA10
FLA9
P9
M10
N10
P10
M11
M12
N13
P13
FLA8/IOCHRDY
FLA7
FLA6
FLA5
FLA4
FLA3
FLA2
FLA1/AUXPWR
FL A0
N14
M13
M14
L12
L13
L14
K14
J12
J13
FLD7
FLD6
FLD5
FLD4
FLD3
FLD2
FLD1
FLD0
J14
H12
H13
H14
G12
F12
F13
F14
M4
L3
F3
C4
F2
F1
G3
H3
H1
J1
H2
J2
A2
A4
C3
J3
C2
G1
B9
A9
A6
C5
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
INTA#
PERR#
SERR#
IDSEL
REQ#
GNT#
RST#
CLK
ISOLATE#
ALTRST #
PME#
EECS
FLCS#
P7
N9
FLCS# ^N9
FLOE#
FLWE#
M8
M9
TEST
TEXEC
TCK
TI
TO
A13
D13
D14
D12
B12
VREF ^C12
RBIAS10 ^B14
RBIAS100 ^B13
C8
CLKRUN#
The ISOLATE signal should be a signal that
X1
X2
N11
P11
B10
is driven low just prior to the PCI bus shutting
A10
down and it should be driven high immediately
C9
following the PCI bus re-activation.
All Vss pins are connected together on the PCB
level. The power on the symbol is broken down
between core power (Vss), local bus power (Vsspl),
transmit power (Vsst), and PCI power (Vsspp) just
for clarity.
PME#
To PIIX4
3VSB
3.3K
3VSB
EEDI
EEDO
EESK
3 _DI
CS ¹
4 _DO
2 _SK
93C46
EECS
VREF: External VREF can be applied here if the internal reference
is not used. The internal reference is recommended, but if an
external reference is implemented, then this will cause the RBIAS
values to change.
1
2
619
1
2
649
RBIAS10 and RBIAS100
should be tuned for your
specific application. The
values shown are a
good starting value.
2
1
25 MHz
22 pF
22 pF
1 K ohm
Pulldown resistors are used
on strapped pins to enable
the NAND tree test mode to
work. The value of 1 K ohm
was chosen strictly on the basis
of Intel’s test fixturing requirements
Other values can be used, but it is
recommended that resistors be used
other than hard strapping the pins.
Figure 32. Reference Schematic Layout (Sheet 2 of 2)
96
Datasheet