82551IT Datasheet, PDF (62/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

82551IT — Networking Silicon
8.1.6
EEPROM Control Register
The EEPROM Control Register is a 32-bit field that enables a read from and a write to the external
EEPROM.
8.1.7
Management Data Interface Control Register
The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and
write bits from the MDI.
Table 22. MDI Control Register
Bits
31:30
29
28
27:26
25:21
20:16
15:0
Description
These bits are reserved and should be set to 0b.
Interrupt Enable. When this bit is set to 1b by software, the 82551IT asserts an interrupt to
indicate the end of an MDI cycle.
Ready. This bit is set to 1b by the 82551IT at the end of an MDI transaction. Software should
set this bit to 0 at the same time the command is written.
Opcode. These bits define the opcode: 01 for MDI write and 10 for MDI read. All other values
(00 and 11) are reserved.
PHY Address. This field of bits contains the PHY address.
PHY Register Address. This field of bits contains the PHY Register Address.
Data. In a write command, software places the data bits in this field, and the 82551IT transfers
the data to the PHY unit. During a read command, the 82551IT reads these bits serially from
the PHY unit, and software reads the data from this location.
8.1.8
Receive Direct Memory Access Byte Count
The Receive DMA Byte Count register keeps track of how many bytes of receive data have been
passed into host memory via DMA.
8.1.9
Flow Control Register
The Flow Control Register contains the following fields:
• Flow Control Command
The Flow Control Command field describes the action of the flow control process (for
example, pause, on, or off).
• Flow Control Threshold
The Flow Control Threshold field contains the threshold value (in other words, the number of
free bytes in the Receive FIFO).
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Datasheet