82551IT Datasheet, PDF (30/102 Pages) Intel Corporation – Fast Ethernet PCI Controller

82551IT — Networking Silicon
5.2.2
6. The MWI Enable bit in the 82551IT Configure command must be set to 1b.
If any one of the above conditions is not true, the 82551IT uses the MW command. If an MWI
cycle has started and one of the conditions is no longer valid (for example, the data space in the
memory buffer is now less than CLS), then the 82551IT terminates the MWI cycle at the end of the
cache line. The next cycle is either an MW or MWI cycle depending on the conditions listed above.
If the 82551IT started a MW cycle and reached a cache line boundary, it either continues or
terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the
82551IT Configure command (byte 3, bit 3). If this bit is set, the 82551IT terminates the MW cycle
and attempts to start a new cycle. The new cycle is an MWI cycle if this bit is set and all of the
above conditions are met. If the bit is not set, the 82551IT continues the MW cycle across the cache
line boundary if required.
5.2.1.2.2 Read Align
The Read Align feature enhances the 82551IT’s performance in cache line oriented systems. In
these particular systems, starting a PCI transaction on a non-cache line aligned address may cause
low performance.
To resolve this performance anomaly, the 82551IT attempts to terminate transmit DMA cycles on a
cache line boundary and start the next transaction on a cache line aligned address. This feature is
enabled when the Read Align Enable bit is set in the 82551IT Configure command (byte 3, bit 2).
If this bit is set, the 82551IT operates as follows:
• When the 82551IT is almost out of resources on the transmit DMA (that is, the transmit FIFO
is almost full), it attempts to terminate the read transaction on the nearest cache line boundary.
• When the arbitration counter’s feature is enabled (in other words, the Transmit DMA
Maximum Byte Count value is set in the Configure command), the 82551IT switches to other
pending DMAs on cache line boundary only.
This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bursts and lower performance. If this feature is used, it is recommended that the CLS
register in PCI Configuration space is set to 8 or 16.
5.2.1.2.3 Error Handling
Data Parity Errors: As an initiator, the 82551IT checks and detects data parity errors that occur
during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register,
bit 6), the 82551IT also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration
Status register, bit 8). In addition, if the error was detected by the 82551IT during read cycles, it
sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
Clock Run Signal
This signal is active in PCI bus operating modes. The Clock Run signal is an open drain I/O signal.
It is used as a bi-directional channel between the host and the devices.
• The host de-asserts the CLK_RUN# signal to indicate that the clock is about to be stopped or
slowed down to a non-operational frequency.
• The host asserts the CLK_RUN# signal when the clock is either running at a normal operating
frequency or about to be started.
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Datasheet