GD82559ER Datasheet, PDF (88/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
EECS
T51
T52
FLA15EESK
T53
T54
FLA13EEDI
10.4.2.5
Figure 30. EEPROM Timings
PHY Timings
Table 28. 10BASE-T NLP Timing Parameters
Symbol
Parameter
T56
T57
T_{nlp_wid}
T_{nlp_per}
NLP Width
NLP Period
Condition Min Typ Max Units
10 Mbps
10 Mbps
100
ns
8
24 ms
T57
T56
Normal Link Pulse
Figure 31. 10BASE-T NLP Timings
Table 29. Auto-Negotiation FLP Timing Parameters
Symbol
Parameter
T58 T_{flp_wid}
FLP Width (clock/data)
T59 T_{flp_clk_clk} Clock Pulse to Clock Pulse Period
T60 T_{flp_clk_dat} Clock Pulse to Data Pulse Period
T61 T_{flp_bur_num} Number of Pulses in one burst
T62 T_{flp_bur_wid} FLP Burst Width
T63 T_{flp_bur_per} FLP Burst Period
Min Typ Max Units
100
ns
111 125 139 µs
55.5 62.5 69.5 µs
17
33
2
ms
8
24 ms
82
Datasheet