GD82559ER Datasheet, PDF (84/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
10.4.2
10.4.2.1
Timing Parameters
Measurement and Test Conditions
Figure 27, Figure 28, and Table 24 define the conditions under which timing measurements are
done. The component test guarantees that all timings are met with minimum clock slew rate
(slowest edge) and voltage swing. The design must guarantee that minimum timings are also met
with maximum clock slew rate (fastest edge) and voltage swing. In addition, the design must
guarantee proper input operation for input voltage swings and slew rates that exceed the specified
test conditions.
V_th
CLK
V_test
V_tl
T_val
OUTPUT
DELAY
V_step
Tri-State
OUTPUT
V_test
V_test
T_on
T_off
Figure 27. Output Timing Measurement Conditions
CLK
INPUT
V_test
T_su
T_h
V_th
V_tl
V_th
V_tl
V_test
inputs
valid
V_test V_max
Figure 28. Input Timing Measurement Conditions
Table 24. Measure and Test Condition Parameters
Symbol
PCI Level
Units
Notes
V_th
0.6V_CC
V
V_tl
0.2V_CC
V
V_test
0.4V_CC
V
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Datasheet