GD82559ER Datasheet, PDF (86/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
Table 26. Flash Timing Parameters
Symbol
Parameter
Min
T35 t_flrwc
Flash Read/Write Cycle Time
150
T36 t_flacc
FLA to Read FLD Setup Time
150
T37 t_flce
FLCS# to Read FLD Setup Time
150
T38 t_floe
T39 t_fldf
T40 t_flas
FLOE# Active to Read FLD Setup Time 120
FLOE# Inactive to FLD Driven Delay
Time
50
FLA Setup Time before FLWE#
5
T41 t_flah
FLA Hold Time after FLWE#
200
T42 t_flcs
FLCS# Hold Time before FLWE#
30
T43 t_flch
FLCS# Hold Time after FLWE#
30
T44 t_flds
FLD Setup Time
150
T45 t_fldh
FLD Hold Time
10
T46 t_flwp
Write Pulse Width
120
T47 t_flwph
Write Pulse Width High
25
T48 t_Mioha
IOCHRDY Hold Time after FLWE# or
FLOE# Active
T49 t_Miohi
IOCHRDY Hold Time after FLWE# or
FLOE# Inactive
0
Max Units
Notes
ns
1, Flash t_AVAV
= 150 ns
ns
1, Flash t_AVQV
= 150 ns
ns
1, Flash t_ELQV
= 150 ns
ns
1, Flash t_GLQV
= 55 ns
ns
1, Flash t_GHQZ
= 35 ns
ns
2, Flash t_AVWL
= 0 ns
ns
2, Flash t_WLAX
= 60 ns
ns
2, Flash t_ELWL
= 20 ns
ns
2, Flash t_WHEH
= 0 ns
ns
2, Flash t_DVWH
= 50 ns
ns
2, Flash t_WHDX
= 10 ns
ns
2, Flash t_WLWH
= 60 ns
ns
2, Flash t_WHWL
= 20 ns
25
ns
ns
NOTES:
1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150
timings.
2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150
timings.
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Datasheet