GD82559ER Datasheet, PDF (77/94 Pages) Intel Corporation – PCI Controller

Networking Silicon — GD82559ER
9.3.8
9.3.9
9.3.10
9.3.11
9.3.12
Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions
Bit(s)
Name
Description
15:0 Premature End of This field contains a 16-bit counter that increments for
Frame
each premature end of frame event. The counter
freezes when full and self-clears on read.
Default
--
R/W
RO
SC
Register 24: 10BASE-T Receive End of Frame Error Counter Bit
Definitions
Bit(s)
Name
15:0 End of Frame
Counter
Description
This is a 16-bit counter that increments for each end
of frame error event. The counter freezes when full
and self-clears on read.
Default
--
R/W
RO
SC
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit
Definitions
Bit(s)
Name
15:0 Jabber Detect
Counter
Description
This is a 16-bit counter that increments for each
jabber detection event. The counter freezes when full
and self-clears on read.
Default
--
R/W
RO
SC
Register 26: Equalizer Control and Status Bit Definitions
Bit(s)
Name
15:0 RFU
Description
Reserved for Future Use
Default
--
R/W
RW
Register 27: PHY Unit Special Control Bit Definitions
Bit(s)
Name
15:3 Reserved
2:0
LED Switch
Control
Description
These bits are reserved and should be set to 0b.
Value
000
001
010
011
100
101
110
111
ACTLED
Activity
Speed
Speed
Activity
Off
Off
On
On
LILED
Link
Collision
Link
Collision
Off
On
Off
On
Default
0
000
R/W
RW
RW
Datasheet
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