GD82559ER Datasheet, PDF (51/94 Pages) Intel Corporation – PCI Controller

6.4
Networking Silicon — GD82559ER
will perform Auto-Negotiation or Parallel Detection with no data packets being transmitted.
Connection is then established either by FLP exchange or Parallel Detection. The PHY unit will
look for both FLPs and link integrity pulses. The following diagram illustrates this process.
Force_Fail
Parallel Detection
Ability detect either by
parallel detect or auto-
negotiation.
Auto-Negotiation
10Base-T or
100Base-TX Link
Ready
FLP capable
Look at Link Pulse;
Auto-Negotiation capable = 0
LINK PASS
Auto-Negotiation capable = 1
Ability Match
Auto-Negotiation Complete bit set
Figure 15. Auto-Negotiation and Parallel Detect
LED Description
The PHY unit supports three LED pins to indicate link status, network activity and network speed.
Each pin can source 10 mA.
• Link: This LED is off until a valid link has been detected. After a valid link has been detected,
the LED will remain on (active-low).
• Activity: This LED blinks on and off when activity is detected on the wire.
• Speed: This LED will be on if a 100BASE-TX link is detected and off if a 10BASE-T link is
detected. If the link fails while in Auto-Negotiation, this LED will keep the last valid link
state. If 100BASE-TX link is forced this LED will be on, regardless of the link status. This
LED will be of if the 10BASE-T link is forced, regardless of the link status.
MDI register 27 in Section 9.3.12, “Register 27: PHY Unit Special Control Bit Definitions” on
page 71 details the information for LED function mapping and support enhancements.
Figure 16 on page 46 provides possible schematic diagrams for configurations using two and three
LEDs.
Datasheet
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