GD82559ER Datasheet, PDF (76/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
Bit(s)
Name
0
Jabber Function
Disable
Description
1 = Jabber disabled
0 = Normal Jabber operation
Default
0
R/W
RW
Register 18: PHY Address Register
Bit(s)
Name
15:5 Reserved
4:0
PHY Address
Description
These bits are reserved and should be set to a
constant ‘0’
These bits are set to the PHY’s address, 00001b.
Default
0
R/W
RO
1
RO
Register 19: 100BASE-TX Receive False Carrier Counter Bit
Definitions
Bit(s)
Name
15:0 Receive False
Carrier
Description
These bits are used for the false carrier counter.
Default
--
R/W
RO
SC
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
Bit(s)
Name
Description
15:0 Disconnect Event This field contains a 16-bit counter that increments for
each disconnect event. The counter freezes when full
and self-clears on read
Default
--
R/W
RO
SC
Register 21: 100BASE-TX Receive Error Frame Counter Bit
Definitions
Bit(s)
Name
15:0 Receive Error
Frame
Description
This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter freezes when full and self-clears
on read.
Default
--
R/W
RO
SC
Register 22: Receive Symbol Error Counter Bit Definitions
Bit(s)
Name
15:0 Symbol Error
Counter
Description
This field contains a 16-bit counter that increments for
each symbol error. The counter freezes when full and
self-clears on read.
In a frame with a bad symbol, each sequential six bad
symbols count as one.
Default
--
R/W
RO
SC
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Datasheet