GD82559ER Datasheet, PDF (44/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
6.1.2.2
Symbol
E
F
I
J
K
T
R
V
V
V
V
H
V
V
V
V
V
V
Table 3. 4B/5B Encoder
5B Symbol Code
4B Nibble Code
11100
11101
11111
11000
10001
01101
00111
00000
00001
00010
00011
00100
00101
00110
01000
01100
10000
11001
1110
1111
Inter Packet Idle Symbol
(No 4B)
1st Start of Packet Symbol
0101
2nd Start of Packet Symbol
0101
1st End of Packet Symbol
2nd End of Packet Symbol
and Flow Control
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
PHY based Flow Control
INVALID
100BASE-TX Scrambler and MLT-3 Encoder
Data is scrambled in 100BASE-TX to reduce electromagnetic emissions during long transmissions
of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and
presents the scrambled data to the MLT-3 encoder. The PHY unit implements the 11-bit stream
cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. The cipher
equation used is:
X[n] = X[n-11] + X[n-9] (mod 2)
The encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the Scrambler
and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZI
coding, but three levels are output instead of two. There are three output levels: positive, negative
and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is maintained
(either positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output
steps to the next level. The order of steps is negative-zero-positive-zero which continues
periodically.
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Datasheet