GD82559ER Datasheet, PDF (26/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be
completed after an 82559ER internal arbitration. (Details on the Configure command are described
in the Software Developer’s Manual.)
The 82559ER, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559ER asserts IRDY# to
support zero wait state burst cycles. The target signals the 82559ER that valid data is ready to be
read by asserting the TRDY# signal.
Write Accesses: The 82559ER performs block transfers to host system memory during frame
reception. In this case, the 82559ER initiates memory write burst cycles to deposit the data, usually
without wait states. The length of a burst is bounded by the system and the 82559ER’s internal
FIFO threshold. The length of a write burst may also be bounded by the value of the Receive DMA
Maximum Byte Count in the Configure command. The Receive DMA Maximum Byte Count value
indicates the maximum number of receive DMA PCI transfers that will be completed before the
82559ER internal arbitration. (Details on the Configure command are described in the Software
Developer’s Manual.)
The 82559ER, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559ER asserts IRDY# to
support zero wait state burst cycles. The 82559ER also drives valid data on AD[31:0] lines during
each data phase (from the first clock and on). The target controls the length and signals completion
of a data phase by de-assertion and assertion of TRDY#.
Cycle Completion: The 82559ER completes (terminates) its initiated memory burst cycles in the
following cases:
• Normal Completion: All transaction data has been transferred to or from the target device
(for example, host main memory).
• Backoff: Latency Timer has expired and the bus grant signal (GNT#) was removed from the
82559ER by the arbiter, indicating that the 82559ER has been preempted by another bus
master.
• Transmit or Receive DMA Maximum Byte Count: The 82559ER burst has reached the
length specified in the Transmit or Receive DMA Maximum Byte Count field in the Configure
command block. (Details relating to this field and the Configure command are described in the
Software Developer’s Manual.)
• Target Termination: The target may request to terminate the transaction with a target-
disconnect, target-retry, or target-abort. In the first two cases, the 82559ER initiates the cycle
again. In the case of a target-abort, the 82559ER sets the Received Target-Abort bit in the PCI
Configuration Status field (PCI Configuration Status register, bit 12) and does not re-initiate
the cycle.
• Master Abort: The target of the transaction has not responded to the address initiated by the
82559ER (in other words, DEVSEL# has not been asserted). The 82559ER simply de-asserts
FRAME# and IRDY# as in the case of normal completion.
• Error Condition: In the event of parity or any other system error detection, the 82559ER
completes its current initiated transaction. Any further action taken by the 82559ER depends
on the type of error and other conditions.
4.2.1.2.1 Memory Write and Invalidate
The 82559ER has four Direct Memory Access (DMA) channels. Of these four channels, the
Receive DMA is used to deposit the large number of data bytes received from the link into system
memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and
Invalidate (MWI) commands. To use MWI, the 82559ER must guarantee the following:
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Datasheet