GD82559ER Datasheet, PDF (10/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
operate independently. Control is switched between the two units according to the microcode
instruction flow. The independence of the Receive and Command units in the micromachine allows
the 82559ER to interleave commands and receive incoming frames, with no real-time CPU
intervention.
The 82559ER contains an interface to an external Flash memory, and external serial EEPROM.
These two interfaces are multiplexed. The Flash interface, which could also be used to connect to
any standard 8-bit device, provides up to 128 Kbytes of addressing to the Flash. Both read and
write accesses are supported. The Flash may be used for remote boot functions, network statistical
and diagnostics functions, and management functions. The Flash is mapped into host system
memory (anywhere within the 32-bit memory address space) for software accesses. It is also
mapped into an available boot expansion ROM location during boot time of the system. More
information on the Flash interface is detailed in Section 4.3, “Parallel Flash Interface” on page 28.
The EEPROM is used to store relevant information for a LAN connection such as node address, as
well as board manufacturing and configuration information. Both read and write accesses to the
EEPROM are supported by the 82559ER. Information on the EEPROM interface is detailed in
Section 4.4, “Serial EEPROM Interface” on page 28.
2.2
FIFO Subsystem Overview
The 82559ER FIFO subsystem consists of a 3 Kbyte transmit FIFO and 3 Kbyte receive FIFO.
Each FIFO is unidirectional and independent of the other. The FIFO subsystem serves as the
interface between the 82559ER parallel side and the serial CSMA/CD unit. It provides a temporary
buffer storage area for frames as they are either being received or transmitted by the 82559ER,
which improves performance:
• Transmit frames can be queued within the transmit FIFO, allowing back-to-back transmission
within the minimum Interframe Spacing (IFS).
• The storage area in the FIFO allows the 82559ER to withstand long PCI bus latencies without
losing incoming data or corrupting outgoing data.
• The 82559ER transmit FIFO threshold allows the transmit start threshold to be tuned to
eliminate underruns while concurrent transmits are being performed (i.e. pending transmits
will not be affected by the change in FIFO threshold).
• The FIFO subsection allows extended PCI burst accesses with zero wait states to or from the
82559ER for both transmit and receive frames. This is because such the transfer is to the FIFO
storage area, rather than directly to the serial link.
• Transmissions resulting in errors (collision detection or data underrun) are retransmitted
directly from the 82559ER FIFO, therey increasing performance and eliminating the need to
re-access this data from the host system.
• Incoming runt receive frames (frames that are less than the legal minimum frame size) can be
discarded automatically by the 82559ER without transferring this faulty data to the host
system, and without host intervention.
• Bad Frames resolution can be selectively left to the 82559ER, or under software control.
4
Datasheet