GD82559ER Datasheet, PDF (40/94 Pages) Intel Corporation – PCI Controller

GD82559ER — Networking Silicon
5.5
5.6
34
TriState
This command set all 82559ER Input and Output pins into a TRI-state (HIGH-Z) mode, all internal
pull-ups and pull-downs are disabled. This mode is entered by setting the following Test Pin Com-
binations: TEST = ‘1, TCK = ‘0, TEXEC = ‘0, TI = ‘1, and resetting the device.
Nand - Tree
The NAND-Tree test mode is the most useful of the asynchronous test modes. The test enables the
placement of the 82559ER to be validated at board test. NAND-Tree was chosen for its speed
advantages. Modern automated test equipment can complete a complete peripheral scan without
support at the board level. This command connects all the outputs of the input-buffers in the device
periphery into a NAND - tree scheme. All the output drivers of the output-buffers except the TOUT
pin, are put into HIGH-Z mode. These pins can then be driven to affect the output of the tree. There
are two separate chains and associated outputs for speed. Any hard strapped pins will prevent the
tester from scanning correctly. This mode is enter by placing the Test Pin in the following Combi-
nations: TEST = ‘1, TCK = ‘0, TEXEC = ‘1, TI = ‘0
There are two nand-tree chains with two separate outputs assigned to FLOE# (Chain 1) and
FLWE# (Chain 2).
Chain Order
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NAND-Tree Output
Table 2. Nand - Tree Chains
Chain 1
Chain 2
RST#
IDSEL
REQ#
AD23
SERR#
AD22
AD21
AD20
AD19
AD18
AD17
C/BE2#
FRAME#
IRDY#
TRDY#
CLK
DEVSEL#
INTA#
LILED
ACTLED#
SPEEDLED
ISOLATE#
ALTRST#
CLKRUN#
AD31
AD30
AD29
AD28
AD27
PME#
AD26
AD25
C/BE3#
AD24
FLD0
FLD1
FLOE#
FLWE#
Datasheet