GD82559ER Datasheet, PDF (43/94 Pages) Intel Corporation – PCI Controller

Networking Silicon — GD82559ER
6.
GD82559ER Physical Layer Functional Description
6.1
6.1.1
6.1.2
6.1.2.1
100BASE-TX PHY Unit
100BASE-TX Transmit Clock Generation
A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY
unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal
Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external
crystal or oscillator must be ± 0.0005% (50 PPM).
100BASE-TX Transmit Blocks
The transmit subsection of the PHY unit accepts nibble-wide data from the CSMA/CD unit. The
transmit subsection passes data unconditionally to the 4B/5B encoder.
The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5-
bit-wide parallel symbols. These symbols are scrambled and serialized into a 125 Mbps bit stream,
converted by the analog transmit driver into a MLT-3 waveform format, and transmitted onto the
Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire.
100BASE-TX 4B/5B Encoder
The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard. Four bits are encoded
according to the transmit 4B/5B lookup table. The lookup table matches a 5-bit code to each 4-bit
code.
The table below illustrates the 4B/5B encoding scheme associated with the given symbol.
Table 3. 4B/5B Encoder
Symbol 5B Symbol Code
4B Nibble Code
0
11110
1
01001
2
10100
3
10101
4
01010
5
01011
6
01110
7
01111
8
10010
9
10011
A
10110
B
10111
C
11010
D
11011
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Datasheet
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