GD82559ER Datasheet, PDF (69/94 Pages) Intel Corporation – PCI Controller

Networking Silicon — GD82559ER
Table 14. 82559ER Statistical Counters
ID
Counter
Description
48 Receive Resource Errors
This counter contains the number of good frames discarded
due to unavailability of resources. Frames intended for a host
whose Receive Unit is in the No Resources state fall into this
category. If the 82559ER is configured to Save Bad Frames
and the status of the received frame indicates that it is a bad
frame, the Receive Resource Errors counter is not updated.
52 Receive Overrun Errors
This counter contains the number of frames known to be lost
because the local system bus was not available. If the traffic
problem persists for more than one frame, the frames that
follow the first are also lost; however, because there is no lost
frame indicator, they are not counted.
56 Receive Collision Detect (CDT)
This counter contains the number of frames that encountered
collisions during frame reception.
60 Receive Short Frame Errors
This counter contains the number of received frames that are
shorter than the minimum frame length. The Receive Short
Frame Errors counter is mutually exclusive to the Receive
Alignment Errors and Receive CRC Errors counters. A short
frame will always increment only the Receive Short Frame
Errors counter.
64 Flow Control Transmit Pause
This counter contains the number of Flow Control frames
transmitted by the 82559ER. This count includes both the Xoff
frames transmitted and Xon (PAUSE(0)) frames transmitted.
68 Flow Control Receive Pause
This counter contains the number of Flow Control frames
received by the 82559ER. This count includes both the Xoff
frames received and Xon (PAUSE(0)) frames received.
72 Flow Control Receive Unsupported This counter contains the number of MAC Control frames
received by the 82559ER that are not Flow Control Pause
frames. These frames are valid MAC control frames that have
the predefined MAC control Type value and a valid address
but has an unsupported opcode.
The Statistical Counters are initially set to zero by the 82559ER after reset. They cannot be preset
to anything other than zero. The 82559ER increments the counters by internally reading them,
incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In
addition, the counters adhere to the following rules:
• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around
to 0.
• The 82559ER updates the required counters for each frame. It is possible for more than one
counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The 82559ER supports all mandatory and recommend statistics functions through
the status of the receive header and directly through these Statistical Counters.
The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This
provides a “snapshot”, in main memory, of the internal 82559ER statistical counters. The 82559ER
supports 21 counters. .
The counters are initialized by power-up reset driven on the ALTRST# pin.
Datasheet
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