80960HA Datasheet, PDF (81/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 59. Bus States
BOFF
!RESET and
!HOLD and
REQUEST
Tb
BOFF
!BOFF
Ta
BOFF
!BOFF and READY and !BLAST or
!BOFF and BTERM and !BLAST or !BOFF and
!HOLD and BLAST and REQUEST and N_XDA = 0
!BOFF and READ and N_rad = 0 or
!BOFF and WRITE and N_wad = 0
W_dCNT = 1
Tdw³
W_dCNT > 1
READ and N_rdd > 0 or
WRITE and N_wdd > 0
Td¹
!BOFF and READ and N_rdd = 0
and !BLAST or !BOFF and
WRITE and N_wdd = 0 and !BLAST or
READY!
READ and N_rad > 0 or
WRITE and N_wad > 0
Taw²
W_aCNT = 1
!BOFF and
BLAST and
N_xda > 0
To
ONCE and
RESET
RESET and
!ONCE
Ti
RESET
W_aCNT > 1
!HOLD and W_xCNT=1
and REQUEST
Trw⁴
W_xCNT > 1
!BOFF and !HOLD and
BLAST andN_xda = 0
and !REQUEST
!HOLD and W_xCNT=1
and !REQUEST
HOLD
W_xCNT=1 and
HOLD
HOLD
Th
!HOLD
NOTE:
!BOFF and
HOLD and BLAST
and N_xda= 0
KEY:
To = ONCE
Ti = IDLE
Th = HOLD
Ta = ADDRESS
Td = DATA
Tb = BOFF’ed
Taw= address to data wait
Tdw= data to data wait
Tdw= data to address wait
REQUEST= One or more
requests in the bus queue.
READ= The current
access is a read.
WRITE= The current
access is a write.
1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as
long as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the
subsequent read access is concurrent with the last data cycle of the access. Because External
Ready Control is disabled for Read Pipelining, the address cycle occurs during BLAST.
2. W_aCNT is decremented during T_aw
3. W_dCNT is decremented during T_dw
4. W_xCNT is decremented during T_rw
Advance Information Datasheet
75