80960HA Datasheet, PDF (68/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus
PMCON
Function
Bit
Value
External
Ready
Control
29
X
x
Burst
28
Enabled
1
Pipe-
Lining
24
ON
1
Bus
Width
23-22
8-Bit
00
Odd
Parity
21
X
x
Parity
Enable
20
Enabled
1
N_XDA
19-16
X
xxxx
N_WDD
15-14
X
xx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1A 2 1
D
1D
1
D 1 A'
D
N_WAD
12-8
X
xxxxx
N_RDD
7-6
1
01
N_RAD
4-0
2
00010
2
1 D' ²
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
W/R
A3:2
BE1/A1,
BE0/A0
D31:0,
DP3:0
WAIT
Valid
Valid
A3:2 = 00, 01, 10, or 11
Valid
A1:0 = 00
A1:0 = 01 A1:0 = 10 A1:0 = 11
Valid
D7:0
Byte 0
D7:0
Byte 1
D7:0
Byte 2
D7:0
Byte 3
In-
valid
In-
valid
In-
valid
In-
valid
D7:0
D'
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
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