80960HA Datasheet, PDF (36/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
4.3
Recommended Connections
Power and ground connections must be made to multiple V_CC and V_SS (GND) pins. Every
80960Hx-based circuit board should include power (V_CC) and ground (V_SS) planes for power
distribution. Every V_CC pin must be connected to the power plane; every V_SS pin must be connected to
the ground plane. Pins identified as “NC” —no connect pins—must not be connected in the system.
Liberal decoupling capacitance should be placed near the 80960Hx. The processor can cause transient
power surges when its output buffers transition, particularly when connected to large capacitive loads.
Low inductance capacitors and interconnects are recommended for best high-frequency electrical
performance. Inductance can be reduced by shortening the board traces between the processor and
decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages
offer the lowest possible inductance.
For reliable operation, always connect unused inputs to an appropriate signal level. In particular,
any unused interrupt (XINT7:0, NMI) input should be connected to V_CC through a pull-up resistor,
as should BTERM if not used. Pull-up resistors should be in the range of 20 KΩ for each pin tied
high. If READY or HOLD are not used, the unused input should be connected to ground. N.C. pins
must always remain unconnected.
4.4
VCC5 Pin Requirements (V_DIFF)
In mixed-voltage systems that drive 80960Hx processor inputs in excess of 3.3 V, the VCC5 pin must
be connected to the system’s 5 V supply. To limit current flow into the VCC5 pin, there is a limit to
the voltage differential between the VCC5 pin and the other V_CC pins. The voltage differential
between the 80960Hx VCC5 pin and its 3.3 V V_CC pins should never exceed 2.25 V. This limit
applies to power-up, power-down, and steady-state operation. Table 20 outlines this requirement.
Meeting this requirement ensures proper operation and guarantees that the current draw into the
VCC5 pin does not exceed the I_CC5 specification.
If the voltage difference requirements cannot be met due to system design limitations, an alternate
solution may be employed. As shown in Figure 7, a minimum of 100 Ω series resistor may be used
to limit the current into the VCC5 pin. This resistor ensures that current drawn by the VCC5 pin
does not exceed the maximum rating for this pin.
Figure 7. VCC5 Current-Limiting Resistor
+5 V (±0.25 V)
VCC5 Pin
100 Ω
(±5%, 0.5 W)
This resistor is not necessary in systems that can guarantee the V_DIFF specification.
In 3.3 V-only systems and systems that drive 80960Hx pins from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V V_CC plane.
Table 20. V_DIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Sym Parameter Min Max Units
Notes
V_DIFF
VCC5-V_CC
Difference
2.25
V
VCC5 input should not exceed V_CC by more than 2.25 V during
power-up and power-down, or during steady-state operation.
30
Advance Information Datasheet