80960HA Datasheet, PDF (66/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
External
Function Ready Burst
Control
Pipe- Bus
Lining Width
Odd
Parity
Parity
Enable
N_XDA
Bit 29
28
24 23-22 21
20 19-16
Value
X Enabled ON 32-Bit
x
1
1
10
X Enabled X
x
1
xxxx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
N_WDD
15-14
X
xx
N_WAD
12-8
X
xxxxx
N_RDD
7-6
0
00
N_RAD
4-0
0
00000
1_A
D
D
D
A' D'
D' ²
D
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
W/R
Valid
Valid
In-
Valid
A3:2
D31:0,
DP3:0
WAIT
00
01
10
11
Valid
Valid
In-
Valid
IN
IN
IN
IN
IN IN
D
D
D
D
D
D
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
60
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