80960HA Datasheet, PDF (65/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
External
Function Ready Burst
Control
Pipe- Bus
Lining Width
Odd
Parity
Parity
Enable
N_XDA
Bit 29
28
24 23-22 21
20 19-16
Value
X Disabled ON 32-Bit
x
0
1
10
X Enabled X
x
1
xxxx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1A
1
A'
1
D
N_WDD
15-14
X
xx
N_WAD
12-8
X
xxxxx
D' 2
N_RDD
7-6
X
xx
N_RAD
4-0
1
00001
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
W/R
Valid
Valid
Invalid
Invalid
A3:2
BE3:0
D31:0,
DP3:0
WAIT
Valid
Valid
IN
D
Invalid
IN
D'
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
Advance Information Datasheet
59