80960HA Datasheet, PDF (67/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON _External
Function Ready
Control
Burst
Pipe-
Lining
Bus
Width
Odd
Parity
Parity
Enable
Bit
29
28
24
23-22
21
20
Value
X
x
Enabled ON
1
1
32-Bit
10
X
Enabled
x
1
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1A 2 1
D
1D
1
CLKIN
N_XDA
19-16
X
xxxx
N_WDD
15-14
X
xx
N_WAD
12-8
X
xxxxx
D1
A' ₂
D
N_RDD
7-6
1
01
N_RAD
4-0
2
00010
1 D' ₂
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
W/R
A3:2
D31:0,
DP3:0
WAIT
BLAST
DT/R
Valid
Valid
In-
valid
In-
valid
00
01
10
11
Valid
In-
valid
IN
IN
IN
IN
IN
D
D
D
D
D'
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
Advance Information Datasheet
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