80960HA Datasheet, PDF (71/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 48. Terminating a Burst with BTERM
CLKIN
Quad-Word Read Request
N_RAD = 0, N_RDD = 0, N_RDA = 0
Ready Enabled
A D 1 A D 1 A D1 D 1
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
W/R
Valid
BLAST
DT/R
DEN
READY
BTERM
A3:2
See Note
00
01
10
11
WAIT
D31:0,
DP3:0
D0
D1
D2
D3
PCHK
Note: READY adds memory access time to data transfers, whether or not the
bus access is a burst access. BTERM interrupts a bus access, whether or not
the bus access has more data transfers pending. Either the READY signal or
the BTERM signal terminates a bus access when the signal is asserted during
the last (or only) data transfer of the bus access.
Advance Information Datasheet
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