80960HA Datasheet, PDF (69/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus
PMCON
External
Function Ready
Control
Burst
Pipe-
Lining
Bus
Width
Odd
Parity
Parity
Enable
N_XDA
Bit 29
28
24
23-22
21
20
19-16
Value
X
x
Enabled ON
1
1
16-Bit
01
X
Enabled
X
x
1
xxxx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
A2 1 D 1 D 1 D
N_WDD
15-14
X
xx
A'
1D
N_WAD
12-8
X
xxxxx
2
CLKIN
N_RDD
7-6
1
01
N_RAD
4-0
2
00010
2
1 D'
ADS
A31:4, SUP,
CT3:0, D/C,
BE0/BLC,
BE3/BHE,
LOCK
W/R
A3:2
BE1/A1
D31:0,
DP3:0
WAIT
BLAST
Valid
Valid
A3:2 = 00 or 10
A3:2 = 01 or 11
Valid
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
Valid
D15:0
A1=1
In-
valid
In-
valid
In-
valid
In-
valid
D15:0
D'
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
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