80960HA Datasheet, PDF (64/102 Pages) Intel Corporation – 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

80960HA/HD/HT
Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
External
Function Ready Burst
Control
Pipe- Bus
Lining Width
Odd
Parity
Parity
Enable
N_XDA
N_WDD
N_WAD
Bit 29
28
24 23-22 21
20 19-16 15-14 12-8
Value
X Disabled ON 32-Bit
x
0
1
10
X Enabled X
x
1
xxxx
X
X
xx
xxxxx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1^A
A'
D
A''
A'''
A''''
D'
D''
D'''
N_RDD
7-6
X
xx
N_RAD
4-0
0
00000
D'''' ₂
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
W/R
Valid
Valid
Valid
Valid
Valid Invalid
Invalid
A3:2
BE3:0
D31:0,
DP3:0
WAIT
Valid
Valid
Valid
Valid
Valid Invalid
IN
IN
IN
IN
IN
D
D'
D''
D'''
D''''
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
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