80C186EC Datasheet, PDF (6/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
PCB
Offset
Function
00H Master PIC Port 0
02H Master PIC Port 1
04H Slave PIC Port 0
06H Slave PIC Port 1
08H
Reserved
0AH SCU Int Req Ltch
0CH DMA Int Req Ltch
0EH TCU Int Req Ltch
10H
Reserved
12H
Reserved
14H
Reserved
16H
Reserved
18H
Reserved
1AH
Reserved
1CH
Reserved
1EH
Reserved
20H WDT Reload High
22H WDT Reload Low
24H WDT Count High
26H WDT Count Low
28H
WDT Clear
2AH
WDT Disable
2CH
Reserved
2EH
Reserved
30H
T0 Count
32H T0 Compare A
34H T0 Compare B
46H
T0 Control
38H
T1 Count
3AH T1 Compare A
3CH T1 Compare B
3EH
T1 Control
PCB
Offset
Function
PCB
Offset
Function
40H
T2 Count
80H
GCS0 Start
42H
T2 Compare
82H
GCS0 Stop
44H
Reserved
84H
GCS1 Start
46H
T2 Control
86H
GCS1 Stop
48H Port 3 Direction
88H
GCS2 Start
4AH Port 3 Pin State
8AH
GCS2 Stop
4CH Port 3 Mux Control
8CH
GCS3 Start
4EH Port 3 Data Latch
8EH
GCS3 Stop
50H Port 1 Direction
90H
GCS4 Start
52H Port 1 Pin State
92H
GCS4 Stop
54H Port 1 Mux Control
94H
GCS5 Start
56H Port 1 Data Latch
96H
GCS5 Stop
58H Port 2 Direction
98H
GCS6 Start
5AH Port 2 Pin State
9AH
GCS6 Stop
5CH Port 2 Mux Control
9CH
GCS7 Start
5EH Port 2 Data Latch
9EH
GCS7 Stop
60H
SCU 0 Baud
A0H
LCS Start
62H
SCU 0 Count
A2H
LCS Stop
64H SCU 0 Control
A4H
UCS Start
66H SCU 0 Status
A6H
UCS Stop
68H SCU 0 RBUF
A8H Relocation Register
6AH
SCU 0 TBUF
AAH
Reserved
6CH
Reserved
ACH
Reserved
6EH
Reserved
AEH
Reserved
70H
SCU 1 Baud
B0H Refresh Base Addr
72H
SCU 1 Count
B2H Refresh Time
74H SCU 1 Control
B4H Refresh Control
76H SCU 1 Status
B6H Refresh Address
78H SCU 1 RBUF
B8H Power Control
7AH
SCU 1 TBUF
BAH
Reserved
7CH
Reserved
BCH
Step ID
7EH
Reserved
BEH
Powersave
Figure 3 Peripheral Control Block Registers
PCB
Offset
Function
C0H DMA 0 Source Low
C2H DMA 0 Source High
C4H DMA 0 Dest Low
C6H DMA 0 Dest High
C8H DMA 0 Count
CAH DMA 0 Control
CCH DMA Module Pri
CEH
DMA Halt
D0H DMA 1 Source Low
D2H DMA 1 Source High
D4H DMA 1 Dest Low
D6H DMA 1 Dest High
D8H DMA 1 Count
DAH DMA 1 Control
DCH
Reserved
DEH
Reserved
E0H DMA 2 Source Low
E2H DMA 2 Source High
E4H DMA 2 Dest Low
E6H DMA 2 Dest High
E8H DMA 2 Count
EAH DMA 2 Control
ECH
Reserved
EEH
Reserved
F0H DMA 3 Source Low
F2H DMA 3 Source High
F4H DMA 3 Dest Low
F6H DMA 3 Dest High
F8H DMA 3 Count
FAH DMA 3 Control
FCH
Reserved
FEH
Reserved
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