80C186EC Datasheet, PDF (32/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
AC SPECIFICATIONS
AC Characteristics 80C186EC-20 80C186EC-13
Symbol
Parameter
Min
Max
Min
Max Unit Notes
INPUT CLOCK
20 MHz
13 MHz
TF
TC
TCH
TCL
TCR
TCF
CLKIN Frequency
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
0
40
0
26 MHz 1
25
%
38 5
%
ns
1
10
%
12
%
ns 1 2
10
%
12
%
ns 1 2
1
10
1
10 ns 1 3
1
10
1
10 ns 1 3
OUTPUT CLOCK
T_CD CLKIN to CLKOUT Delay
T
CLKOUT Period
T_PH CLKOUT High Time
T_PL CLKOUT Low Time
T_PR CLKOUT Rise Time
T_PF CLKOUT Fall Time
OUTPUT DELAYS
0
17
0
23 ns 1 4
2 TC
2 TC ns 1
(T 2) ^b 5 (T 2) ^a 5 (T 2) ^b 5 (T 2) ^a 5 ns 1
(T 2) ^b 5 (T 2) ^a 5 (T 2) ^b 5 (T 2) ^a 5 ns 1
1
6
1
6
ns 1 5
1
6
1
6
ns 1 5
T_CHOV1 ALE S2 0 DEN DT R
BHE (RFSH) LOCK A19 16
3
20
3
25 ns 1 4 6 7
T_CHOV2 GCS7 0 LCS UCS
RD WR NCS WDTOUT
3
23
3
30 ns 1 4 6 8
T_CLOV1 BHE (RFSH) DEN LOCK RESOUT
HLDA T0OUT T1OUT
3
20
3
25 ns 1 4 6
T_CLOV2 RD WR GSC7 0 LCS UCS AD15 0
3
23
3
30 ns 1 4 6
(AD7 0 A15 8) NCS INTA S2 0 A19 16
T_CHOF RD WR BHE (RFSH) DT R LOCK
S2 0 A19 16
0
25
0
30 ns 1
T_CLOF DEN AD15 0 (AD7 0 A15 8)
INPUT REQUIREMENTS
0
25
0
30 ns 1
T_CHIS TEST NMI T1IN T0IN READY
10
CTS1 0 BCLK1 0 P3 4 P3 5
10
ns 1 9
T_CHIH TEST NMI T1IN T0IN READY
3
CTS1 0 BCLK1 0 P3 4 P3 5
3
ns 1 9
T_CLIS AD15 0 (AD7 0) READY
10
T_CLIH AD15 0 (AD7 0) READY
3
T_CLIS HOLD RESIN PEREQ ERROR DRQ3 0 10
T_CLIH HOLD RESIN REREQ ERROR DRQ3 0 3
10
ns 1 10
3
ns 1 10
10
ns 1 9
3
ns 1 9
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at V_IH for high time V_IL for low time
3 Only required to guarantee I_CC Maximum limits are bounded by T_C T_CH and T_CL
4 Specified for a 50 pF load see Figure 14 for capacitive derating information
5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF
6 See Figure 15 for rise and fall times
7 T_CHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
8 T_CHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
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