80C186EC Datasheet, PDF (29/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
I_CC versus Frequency and Voltage
The I_CC consumed by the processor is composed of
two components
1 I_PD The quiescent current that represents inter-
nal device leakage Measured with all inputs at
either V_CC or ground and no clock applied
2 I_CCS The switching current used to charge and
discharge internal parasitic capacitance when
changing logic levels I_CCS is related to both the
frequency of operation and the device supply
voltage (V_CC) I_CCS is given by the formula
Power e V I e V² C_DEV f
I_CCS e V C_DEV f
Where
V ^e Supply Voltage (V_CC)
C_DEV ^e Device Capacitance
f ^e Operating Frequency
Measuring C_PD on a device like the 80C186EC
would be difficult Instead C_PD is calculated using
the above formula with I_CC values measured at
known V_CC and frequency Using the C_PD value the
user can calculate I_CC at any voltage and frequency
within the specified operating range
Example Calculate typical I_CC at 14 MHz 5 2V V_CC
I_CC e I_PD a I_CCS
e 0 1 mA a 5 2V
e 56 2 mA
0 77
14 MHz
PDTMR Pin Delay Calculation
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize
NOTE
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset while in Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized
To calculate the value of capacitor to use to provide
a desired delay use the equation
440 c t e C_PD (5V 25 C)
Where
t ^e desired delay in seconds
C_PD ^e capacitive load on PDTMR in microfarads
Example For a delay of 300 ms a capacitor value of
C_PD ^e 440 ^c (300 ^c 10^{b6 e} 0 132 mF is required
Round up to a standard (available) capacitor value
NOTE
The above equation applies to delay time longer
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay A delay
variance of ^a50% to ^b25% can occur due to
temperature voltage and device process ex-
tremes In general higher V_CC and or lower tem-
peratures will decrease delay time while lower V_CC
and or higher temperature will increase delay time
Parameter
CPD
CPD (Idle Mode)
Typical
0 77
0 55
Max
Units
Notes
1 37
mA V MHz
12
0 96
mA V MHz
12
NOTES
1 Maximum C_PD is measured at b40 C with all outputs loaded as specified in the AC test conditions and the device in reset
(or Idle Mode) Due to tester limitations CLKOUT and OSCOUT also have 50 pF loads that increase I_CC by V C F
2 Typical C_PD is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode)
29