80C186EC Datasheet, PDF (13/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
Pin Name
PEREQ
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
T0OUT
T1OUT
T0IN
T1IN
INT7 0
INTA
P3 5
P3 4
P3 3 DMAI1
P3 2 DMAI0
Pin
Type
I
O
O
O
O
I
I
O
IO
O
Input
Type
A(L)
Table 2 Pin Descriptions (Continued)
Output
States
Pin Description
Processor Extension REQuest signals that a data
transfer between an 80C187 Numerics Processor
Extension and Memory is pending Systems not using an
80C187 must tie this pin to V_SS This signal does not exist
on the 80C188EC 80L188EC
H(1)
Upper Chip Select will go active whenever the address of
R(1)
a memory or I O bus cycle is within the address range
I(1)
programmed by the user After reset UCS is configured to
P(1)
be active for memory accesses between 0FFC00H and
0FFFFFH
H(1)
Lower Chip Select will go active whenever the address of
R(1)
a memory or I O bus cycle is within the address range
I(1)
programmed by the user LCS is inactive after a reset
P(1)
H(X) H(1)
R(1)
I(X) I(1)
P(X) P(1)
These pins provide a multiplexed function If enabled
each pin can provide a General purpose Chip Select
output which will go active whenever the address of a
memory or I O bus cycle is within the address limitations
programmed by the user When not programmed as a
Chip-Select each pin may be used as a general purpose
output port
H(Q)
R(1)
I(Q)
P(X)
Timer OUTput pins can be programmed to provide single
clock or continuous waveform generation depending on
the timer mode selected
A(L)
Timer INput is used either as clock or control signals
A(E)
depending on the timer mode selected This pin may be
either level or edge sensitive depending on the
programming mode
A(L)
Maskable INTerrupt input will cause a vector to a specific
A(E)
Type interrupt routine The INT6 0 pins can be used as
cascade inputs from slave 8259A devices The INT pins
can be configured as level or edge sensitive
H(1)
INTerrupt Acknowledge output is a handshaking signal
R(1)
used by external 82C59A Programmable Interrupt
I(1)
Controllers
P(1)
A(L)
H(X)
Bidirectional open-drain port pins
R(Z)
I(X)
H(X)
H(X)
R(0)
I(Q)
P(X)
DMA Interrupt output goes active to indicate that the
channel has completed a transfer DMAI1 and DMAI0 are
multiplexed with output only port functions
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
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