80C186EC Datasheet, PDF (34/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
AC Characteristics 80L186EC13 (Continued)
NOTES
6 See Figure 15 for rise and fall times
7 T_CHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
8 T_CHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
AC Characteristics 80L186EC16 (Operating Temperature 0 C to 70 C)
Symbol
Parameter
Min
Max
INPUT CLOCK
16 MHz
T_F
CLKIN Frequency
T_C
CLKIN Period
T_CH
CLKIN High Time
T_CL
CLKIN Low Time
T_CR
CLKIN Rise Time
T_CF
CLKIN Fall Time
OUTPUT CLOCK
0
32
31 25
%
13
%
13
%
1
10
1
10
T_CD
CLKIN to CLKOUT Delay
T
CLKOUT Period
T_PH
CLKOUT High Time
T_PL
CLKOUT Low Time
T_PR
CLKOUT Rise Time
T_PF
CLKOUT Fall Time
OUTPUT DELAYS
0
(T 2) ^b 5
(T 2) ^b 5
1
1
20
2 TC
(T 2) ^a 5
(T 2) ^a 5
9
9
T_CHOV1 S2 0 DT R BHE LOCK
3
25
T_CHOV2 LCS UCS DEN A19 16 RD WR NCS
3
30
WDTOUT ALE
T_CHOV3 GCS7 0
3
32
T_CLOV1 LOCK RESOUT HLDA T0OUT T1OUT
3
25
T_CLOV2 RD WR AD15 0 (AD7 0 A15 8) BHE
3
30
(RFSH) NCS INTA DEN
T_CLOV3
T_CLOV4
T_CHOF
GSC7 0 LCS UCS
S2 0 A19 16
RD WR BHE (RFSH) DT R LOCK
S2 0 A19 16
3
32
3
34
0
28
T_CLOF
DEN AD15 0 (AD7 0 A15 8)
INPUT REQUIREMENTS
0
32
T_CHIS
TEST NMI T1IN T0IN READY
15
CTS1 0 BCLK1 0 P3 4 P3 5
T_CHIH
TEST NMI T1IN T0IN READY
3
CTS1 0 BCLK1 0 P3 4 P3 5
T_CLIS
AD15 0 (AD7 0) READY
15
T_CLIH
AD15 0 (AD7 0) READY
3
T_CLIS
HOLD RESIN PEREQ ERROR DRQ3 0
15
T_CLIH
HOLD RESIN PEREQ ERROR DRQ3 0
3
34
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
12
12
13
13
14
1
1
1
15
15
1467
1468
146
146
146
146
146
1
1
19
19
1 10
1 10
19
19