80C186EC Datasheet, PDF (11/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
Pin Name
A18 S5
A17 S4
A16 S3
(A15 8)
AD15 CAS2
AD14 CAS1
AD13 CAS0
AD12 0
(AD7 0)
S2 0
ALE
BHE
(RFSH)
Pin
Type
IO
IO
IO
O
O
O
Input
Type
A(L)
S(L)
S(L)
Table 2 Pin Descriptions (Continued)
Output
States
Pin Description
H(Z)
R(WH)
I(0)
P(0)
These pins drive address information during the address
phase of the bus cycle During T2 and T3 these pins drive
status information (which is always 0 on the 80C186EC)
These pins are used as inputs during factory test driving
these pins low during reset will cause unspecified operation
On the 80C188EC A15 8 provide valid address information
for the entire bus cycle
H(Z)
R(Z)
I(0)
P(0)
These pins are part of the multiplexed ADDRESS and DATA
bus During the address phase of the bus cycle address bits
15 through 13 are presented on these pins and can be
latched using ALE Data information is transferred during the
data phase of the bus cycle Pins AD15 13 CAS2 0 drive the
82C59 slave address information during interrupt
acknowledge cycles
H(Z)
R(Z)
I(0)
P(0)
These pins provide a multiplexed ADDRESS and DATA bus
During the address phase of the bus cycle address bits 0
through 12 (0 through 7 on the 80C188EC) are presented on
the bus and can be latched using ALE Data information is
transferred during the data phase of the bus cycle
H(Z)
R(1)
I(1)
P(1)
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
S2 S1 S0
Bus Cycle Initiated
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt Acknowledge
Read I O
Write I O
Processor HALT
Instruction Queue Fetch
Read Memory
Write Memory
Passive (No bus activity)
H(0) Address Latch Enable output is used to strobe address
R(0) information into a transparent type latch during the address
I(0)
phase of the bus cycle
P(0)
H(Z)
R(Z)
I(1)
P(1)
Byte High Enable output to indicate that the bus cycle in
progress is transferring data over the upper half of the data
bus BHE and A0 have the following logical encoding
A0 BHE
Encoding (for 80C186EC
80L186EC only)
0
0
0
1
1
0
1
1
Word transfer
Even Byte transfer
Odd Byte transfer
Refresh operation
On the 80C188EC 80L188EC RFSH is asserted low to
indicate a refresh bus cycle
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
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