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80C186EC Datasheet, PDF (33/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
80C186EC 188EC 80L186EC 188EC
AC Characteristics 80L186EC13
Symbol
Parameter
INPUT CLOCK
TF
CLKIN Frequency
TC
CLKIN Period
TCH
CLKIN High Time
TCL
CLKIN Low Time
TCR
CLKIN Rise Time
TCF
CLKIN Fall Time
OUTPUT CLOCK
TCD
CLKIN to CLKOUT Delay
T
CLKOUT Period
TPH
CLKOUT High Time
TPL
CLKOUT Low Time
TPR
CLKOUT Rise Time
TPF
CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1
TCHOV2
S2 0 DT R BHE LOCK
LCS UCS DEN A19 16 RD WR NCS
WDTOUT ALE
TCHOV3
TCLOV1
TCLOV2
GCS7 0
LOCK RESOUT HLDA T0OUT T1OUT
RD WR AD15 0 (AD7 0 A15 8) BHE
(RFSH) NCS INTA DEN
TCLOV3
TCLOV4
TCHOF
GSC7 0 LCS UCS
S2 0 A19 16
RD WR BHE (RFSH) DT R LOCK
S2 0 A19 16
TCLOF
DEN AD15 0 (AD7 0 A15 8)
INPUT REQUIREMENTS
TCHIS
TEST NMI T1IN T0IN READY
CTS1 0 BCLK1 0 P3 4 P3 5
TCHIH
TEST NMI T1IN T0IN READY
CTS1 0 BCLK1 0 P3 4 P3 5
TCLIS
TCLIH
TCLIS
TCLIH
AD15 0 (AD7 0) READY
AD15 0 (AD7 0) READY
HOLD RESIN PEREQ ERROR DRQ3 0
HOLD RESIN REREQ ERROR DRQ3 0
Min
Max
13 MHz
0
26
38 5
%
15
%
15
%
1
10
1
10
0
(T 2) b 5
(T 2) b 5
1
1
20
2 TC
(T 2) a 5
(T 2) a 5
10
10
3
28
3
32
3
34
3
28
3
32
3
34
3
37
0
30
0
35
20
3
20
3
20
3
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at VIH for high time VIL for low time
3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL
4 Specified for a 50 pF load see Figure 14 for capacitive derating information
5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
12
12
13
13
14
1
1
1
15
15
1467
1468
146
146
146
146
146
1
1
19
19
1 10
1 10
19
19
33