80C186EC Datasheet, PDF (36/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
Relative Timings (80C186EC-25 20 13 80L186EC-16 13)
NOTES
1 Assumes equal loading on both pins
2 Can be extended using wait states
3 Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the
8259A module going active This is not directly measureable by the user For interrupt pin INT7 the delay from an active
signal to an active input to the CPU would actually be twice the T_IRES value since the signal must pass through two 8259A
modules
4 See INTA Cycle Waveforms for definition
5 To guarantee interrupt is not spurious
Serial Port Mode 0 Timings (80C186EC-25 20 13 80L186EC-16 13)
Symbol
Parameter
Min
Max
Unit Notes
RELATIVE TIMINGS
T_XLXL
TXD Clock Period
T (n ^a 1)
ns
12
T_XLXH
TXD Clock Low to Clock High (N ^l 1)
2T ^b 35
2T ^a 35
ns
1
T_XLXH
TXD Clock Low to Clock High (N ^e 1)
T ^b 35
T ^a 35
ns
1
T_XHXL
TXD Clock High to Clock Low (N ^l 1) (n ^b 1) T ^b 35 (n ^b 1) T ^a 35 ns
12
T_XHXL
TXD Clock High to Clock Low (N ^e 1)
T ^b 35
T ^a 35
ns
1
T_QVXH
RXD Output Data Setup to TXD
Clock High (N ^l 1)
(n ^b 1)T ^b 35
ns
12
T_QVXH
RXD Output Data Setup to TXD
Clock High (N ^e 1)
T ^b 35
ns
1
T_XHQX
RXD Output Data Hold after TXD
Clock High (N ^l 1)
2T ^b 35
ns
1
T_XHQX
RXD Output Data Hold after TXD
Clock High (N ^e 1)
T ^b 35
ns
1
T_XHQZ
RXD Output Data Float after Last
TXD Clock High
T ^a 20
ns
1
T_DVXH
RXD Input Data Setup to TXD
Clock High
T ^a 20
ns
1
T_XHDX RXD Input Data Setup after TXD
0
Clock High
ns
1
NOTES
1 See Figure 13 for Waveforms
2 n is the value in the BxCMP register ignoring the ICLK bit
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