80C186EC Datasheet, PDF (31/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
AC SPECIFICATIONS
AC Characteristics 80C186EC25 (Continued)
Symbol
Parameter
SYNCHRONOUS INPUTS
T_CHIS
TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0
P2 6 P2 7
T_CHIH
T_CLIS
T_CLIH
T_CLIS
T_CLIH
TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0
AD15 0 (AD7 0) READY
READY AD15 0 (AD7 0)
HOLD PEREQ ERROR
HOLD PEREQ ERROR
25 MHz
Min Max
10
3
10
3
10
3
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at V_IH for high time V_IL for low time
3 Only required to guarantee I_CC Maximum limits are bounded by T_C T_CH and T_CL
4 Specified for a 50 pF load see Figure 13 for capacitive derating information
5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF
6 See Figure 14 for rise and fall times
7 T_CHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
8 T_CHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
Units
ns
ns
ns
ns
ns
ns
Notes
19
19
1 10
1 10
19
19
31