80C186EC Datasheet, PDF (54/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
INSTRUCTION SET SUMMARY (Continued)
Function
Format
LOGIC (Continued)
XOR e Exclusive or
Reg memory and register to either
0 0 1 1 0 0 d w mod reg r m
Immediate to register memory
1 0 0 0 0 0 0 w mod 1 1 0 r m
Immediate to accumulator
0011010w
data
NOT e Invert register memory
STRING MANIPULATION
MOVS e Move byte word
1 1 1 1 0 1 1 w mod 0 1 0 r m
1010010w
CMPS e Compare byte word
1010011w
SCAS e Scan byte word
1010111w
LODS e Load byte wd to AL AX
1010110w
STOS e Store byte wd from AL AX
1010101w
INS e Input byte wd from DX port
0110110w
OUTS e Output byte wd to DX port
0110111w
Repeated by count in CX (REP REPE REPZ REPNE REPNZ)
MOVS e Move string
11110010 1010010w
CMPS e Compare string
1111001z 1010011w
SCAS e Scan string
1111001z 1010111w
LODS e Load string
11110010 1010110w
STOS e Store string
11110010 1010101w
INS e Input string
11110010 0110110w
data
data if we1
data if we1
80C186EC
Clock
Cycles
80C188EC
Clock
Cycles
Comments
3 10
4 16
34
3 10
14
22
15
12
10
14
14
3 10
4 16
34
3 10
14
22
15
12
10
14
14
8 16-bit
8a8n
5a22n
5a15n
6a11n
6a9n
8a8n
8a8n
5a22n
5a15n
6a11n
6a9n
8a8n
OUTS e Output string
CONTROL TRANSFER
CALL e Call
Direct within segment
Register memory
indirect within segment
11110010 0110111w
11101000
11111111
disp-low
mod 0 1 0 r m
disp-high
8a8n
8a8n
15
13 19
19
17 27
Direct intersegment
10011010
segment offset
segment selector
23
31
Indirect intersegment
JMP e Unconditional jump
Short long
Direct within segment
Register memory
indirect within segment
1 1 1 1 1 1 1 1 mod 0 1 1 r m (mod i 11)
11101011
11101001
11111111
disp-low
disp-low
mod 1 0 0 r m
disp-high
38
54
14
14
11 17
14
14
11 21
Direct intersegment
11101010
segment offset
segment selector
14
14
Indirect intersegment
1 1 1 1 1 1 1 1 mod 1 0 1 r m (mod i 11)
Shaded areas indicate instructions not available in 8086 8088 microsystems
26
34
NOTE
Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
54