80C186EC Datasheet, PDF (52/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EC 188EC 80L186EC 188EC
INSTRUCTION SET SUMMARY (Continued)
Function
Format
DATA TRANSFER (Continued)
SEGMENT e Segment Override
CS
SS
DS
ES
ARITHMETIC
ADD e Add
Reg memory with register to either
Immediate to register memory
Immediate to accumulator
ADC e Add with carry
Reg memory with register to either
Immediate to register memory
Immediate to accumulator
INC e Increment
Register memory
Register
SUB e Subtract
Reg memory and register to either
Immediate from register memory
Immediate from accumulator
SBB e Subtract with borrow
Reg memory and register to either
Immediate from register memory
Immediate from accumulator
DEC e Decrement
Register memory
Register
CMP e Compare
Register memory with register
Register with register memory
Immediate with register memory
Immediate with accumulator
NEG e Change sign register memory
AAA e ASCII adjust for add
DAA e Decimal adjust for add
AAS e ASCII adjust for subtract
DAS e Decimal adjust for subtract
00101110
00110110
00111110
00100110
000000dw
100000sw
0000010w
mod reg r m
mod 0 0 0 r m
data
000100dw
100000sw
0001010w
mod reg r m
mod 0 1 0 r m
data
1111111w
0 1 0 0 0 reg
mod 0 0 0 r m
001010dw
100000sw
0010110w
mod reg r m
mod 1 0 1 r m
data
000110dw
100000sw
0001110w
mod reg r m
mod 0 1 1 r m
data
1111111w
0 1 0 0 1 reg
mod 0 0 1 r m
0011101w
0011100w
100000sw
0011110w
1111011w
00110111
00100111
00111111
00101111
mod reg r m
mod reg r m
mod 1 1 1 r m
data
mod 0 1 1 r m
data
data if we1
data
data if we1
data
data if we1
data
data if we1
data
data if we1
data if s we01
data if s we01
data if s we01
data if s we01
data if s we01
80C186EC
Clock
Cycles
80C188EC
Clock
Cycles
Comments
2
2
2
2
2
2
2
2
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
3 10
3 10
34
3 10
8
4
7
4
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
3 10
3 10
34
3 10
8
4
7
4
8 16-bit
8 16-bit
8 16-bit
8 16-bit
8 16-bit
MUL e Multiply (unsigned)
1 1 1 1 0 1 1 w mod 100 r m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
26 – 28
35 – 37
32 – 34
41 – 43
26 – 28
35 – 37
32 – 34
41 – 43
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
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