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80C186EC Datasheet, PDF (35/57 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
80C186EC 188EC 80L186EC 188EC
AC Characteristics 80L186EC16 (Continued)
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at VIH for high time VIL for low time
3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL
4 Specified for a 50 pF load see Figure 14 for capacitive derating information
5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF
6 See Figure 15 for rise and fall times
7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
8 TCHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
Relative Timings (80C186EC-25 20 13 80L186EC-16 13)
Symbol
Parameter
Min
Max
RELATIVE TIMINGS
TLHLL
TAVLL
TPLLL
TLLAX
TLLWL
TLLRL
TWHLH
TAFRL
TRLRH
TWLWH
TRHAX
TWHDX
TWHPH
TRHPH
TPHPL
ALE Active Pulse Width
AD Valid Setup before ALE Falls
Chip Select Valid before ALE Falls
AD Hold after ALE Falls
ALE Falling to WR Falling
ALE Falling to RD Falling
WR Rising to Next ALE Rising
AD Float to RD Falling
RD Active Pulse Width
WR Active Pulse Width
RD Rising to Next Address Active
Output Data Hold after WR Rising
WR Rise to Chip Select Rise
RD Rise to Chip Select Rise
Chip Select Inactive to Next Chip
Select Active
T b 15
T b 10
T b 10
T b 10
T b 15
T b 15
T b 10
0
2T b 5
2T b 5
T b 15
T b 15
T b 10
T b 10
T b 10
TOVRH
TRHOX
TIHIL
ONCE Active Setup to RESIN Rising
ONCE Hold after RESIN Rise
INTA High to Next INTA Low
during INTA Cycle
T
T
4T b 5
TILIH
TCVIL
INTA Active Pulse Width
CAS2 0 Setup before 2nd INTA
Pulse Low
2T b 5
8T
TILCX
CAS2 0 Hold after 2nd INTA Pulse Low
4T
TIRES
Interrupt Resolution Time
150
TIRLH
IR Low Time to Reset Edge Detector
50
TIRHIF
IR Hold Time after 1st INTA Falling
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1
2
2
1
1
1
4
24
24
24
3
45
35