DD28F032SA Datasheet, PDF (5/49 Pages) Intel Corporation – 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY

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1.0 PRODUCT OVERVIEW
The DD28F032SA is a high-performance 32-Mbit
(33,554,432-bit) block erasable nonvolatile random
access memory organized as either 2 Mword x 16,
or 4 Mbyte x 8. The DD28F032SA is built using
two 28F016SA chips encapsulated in a single
56- lead TSOP Type I package. The DD28F032SA
includes sixty-four 64-KB (65,536) blocks or sixty-
four 32-KW (32,768) blocks.
The DD28F032SA architecture allows operations
to be performed on a single, 16-Mbit chip at a
time.
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and results in greater
product reliability and ease of use.
Among the significant enhancements on the
DD28F032SA:
• 3.3V Low Power Capability
• Improved Program Performance
• Dedicated Block Program/Erase Protection
A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/program
operation.
The DD28F032SA will be available in a 56-lead,
1.2 mm thick, 14 mm x 20 mm Dual Die TSOP
Type I package. This form factor and pinout allow
for very high board layout densities. The
DD28F032SA is pinout and footprint compatible
with the 28F016SA.
Two Command User Interfaces (CUI) serve as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal algorithm automation allows word/byte
programs and block erase operations to be
executed using a two-write command sequence to
the CUI in the same way as the 28F016SA
16-Mbit FlashFile memory.
A super-set of commands has been added to the
basic 28F008SA (8-Mbit FlashFile memory)
command-set to achieve higher program
performance and provide additional capabilities.
DD28F032SA
These new commands and features include:
• Page Buffer Writes to Flash
• Command Queueing Capability
• Automatic Data Programs during Erase
• Software Locking of Memory Blocks
• Two-Byte Successive Programs in 8-bit
Systems
• Erase All Unlocked Blocks
These operations can only be performed on one
16-Mbit device at a time. If the WSM is busy
performing an operation, the system should not
attempt to select the other device.
Writing of memory data is performed in either byte
or word increments typically within 6 µs, a 33%
improvement over the 28F008SA. A block erase
operation erases one of the 64 blocks in typically
0.6 sec, independent of the other blocks, which is
a 65% improvement over the 28F008SA.
Each block can be written and erased a minimum
of 100,000 cycles. Systems can achieve typically
1 million block erase cycles by providing wear-
leveling algorithms and graceful block retirement.
These techniques have already been employed in
many flash file systems. Additionally, wear leveling
of block erase cycles can be used to minimize the
program/erase performance differences across
blocks.
The DD28F032SA incorporates two Page Buffers
of 256 bytes (128 words) on each 28F016SA to
allow page data programs. This feature can
improve a system program performance by up to
4.8 times over previous flash memory devices.
All operations are started by a sequence of
command writes to the device. Three Status
Registers (described in detail later) and a RY/BY#
output pin provide information on the progress of
the requested operation.
The DD28F032SA allows queueing of the next
operation while the memory executes the current
operation. This eliminates system overhead when
writing several bytes in a row to the array or
erasing several blocks at the same time. The
DD28F032SA can also perform program
operations to one block of memory while
performing erase of another block. However,
simultaneous program and/or erase operations are
not allowed on both 28F016SA devices. See
Modes of Operation, Section 3.0.
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