DD28F032SA Datasheet, PDF (14/49 Pages) Intel Corporation – 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY

DD28F032SA
E
5.3 28F008SA Compatible Mode Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Command
Notes Oper Addr Data Oper Addr Data
Read Array
Write
X
xxFFH Read
AA
AD
Intelligent Identifier
1
Write
X
xx90H Read
IA
ID
Read Compatible Status Register
2
Write
X
xx70H Read
X
CSRD
Clear Status Register
3
Write
X
xx50H
Word/Byte Program
Write
X
xx40H Write
PA
PD
Alternate Word/Byte Program
Write
X
xx10H Write
PA
PD
Block Erase/Confirm
Write
X
xx20H Write
BA xxD0H
Erase Suspend/Resume
Write
X
xxB0H Write
X
xxD0H
ADDRESS
A = Array Address
BA = Block Address
IA = Identifier Address
PA = Program Address
X = Don’t Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
PD = Program Data
NOTES:
1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters data program, block erase, or suspend operations.
3. Clears CSR.3, CSR.4 and CSR.4. Also clears GSR.4 and all BSR.4 and BSR.2 bits.
4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.
See Status Register definitions.
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