DD28F032SA Datasheet, PDF (32/49 Pages) Intel Corporation – 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY

DD28F032SA
6.7 Power-Up and Reset Timings
E
V_CC Power-Up
RP#
(P)
3/5#
(Y)
V_CC
0V
(3V,5V)
CE_X #
Address
(A)
Data
(Q)
t _YHPH
3.3V
t _YLPH
t _PLYL
5.0V
4.5V
t _PL5V
t_PHEL3
Valid
t _AVQV
Valid 3.3V Outputs
t _PHQV
t _PHEL5
Valid
t _AVQV
Valid 5.0V Outputs
t _PHQV
0490-13
Figure 13. V_CC Power-Up and RP# Reset Waveforms
Symbol
Parameter
Notes Min Max Units
t_PLYL
t_PLYH
RP# Low to 3/5# Low (High)
0
µs
t_YLPH
t_YHPH
3/5# Low (High) to RP# High
1
2
µs
t_PL5V
RP# Low to V_CC at 4.5V Minimum (to V_CC at
2
0
µs
t_PL3V
3.0V min or 3.6V max)
t_PHEL3
RP# High to CE# Low (3.3V VCC)
1
500
t_PHEL5
RP# High to CE# Low (5V VCC)
1
330
t_AVQV
Address Valid to Data Valid for V_CC = 5.0V ± 10%
3
80
ns
t_PHQV
RP# High to Data Valid for V_CC = 5.0V ± 10%
3
480
ns
NOTES:
CE₀#, CE_X# and OE# are switched low after Power-Up.
1. The tYLPH/tYHPH and tPHEL3/tPHEL5 times must be strictly followed to guarantee all other read and program specifications.
2. The power supply may start to switch concurrently with RP# going low.
3. The address access time and RP# high to data valid time are shown for the DD28F032SA-80 and 5.0V V_CC operation.
Refer to the AC Characteristics-Read Only Operations for 3.3V V_CC operation and all other speed options.
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