DD28F032SA Datasheet, PDF (36/49 Pages) Intel Corporation – 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY

DD28F032SA
E
DEEP
POWER-DOWN
VIH
ADDRESSES (A)
NOTE 1 ^V IL
V _IH
ADDRESSES (A)
NOTE 2 ^V IL
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
t _AVAV
t _AVAV
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
WRITE READ EXTENDED
REGISTER COMMAND
A _IN
t _AVWH
A _IN
t _AVWH
t _WHAX
t _WHAX
NOTE 3
V _IH
CEx # (E)
NOTE 4 ^V IL
V _IH
OE# (G) _{V IL}
t _ELWL
t _WHEH
t _WHGL
READ EXTENDED
STATUS REGISTER DATA
A=RA
READ COMPATIBLE
STATUS REGISTER DATA
V _IH
WE# (W)
V _IL
t _WHWL
t _WLWH
t _DVWH
t _WHDX
V _IH
HIGH Z
DATA (D/Q)
V _IL
t _PHWL
D _IN
D _IN
t _WHQV1,2
D _IN
t _GHWL
D _OUT
D _IN
V _OH
RY/BY# (R)
V _OL
t _WHRL
V _IH
RP# (P)
V _IL
t _RHPL
NOTE 5
VPPH
t _VPWH
t _QVVL
V _PP(V)
VPPL
V _IH
V _IL
0490-14
NOTES:
1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/block erase operations.
4. For 28F016SA No. 1: CE_X# is defined as the latter of CE₀# or CE₁# going low, or the first of CE₀# or CE₁# going high.
For 28F016SA No. 2: CE_X# is defined as the latter of CE₀# or CE₂# going low, or the first of CE₀# or CE₂# going high
5. RP# low transition is only to show t_RHPL; not valid for above Read and Program cycles.
Figure 14. AC Waveforms for Command Write Operations
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