DD28F032SA Datasheet, PDF (21/49 Pages) Intel Corporation – 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY

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DD28F032SA
6.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE tELQV time(t) from CEX# (E) going low (L) to the outputs (Q) becoming valid (V)
tOE tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)
tACC tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tDH tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
A
Address Inputs
D
Data Inputs
Q
Data Outputs
E
CE_X# (Chip Enable)
F
BYTE# (Byte Enable)
G
OE# (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY/BY# (Ready Busy)
V
Any Voltage Level
Y
3/5# Pin
5V
V_CC at 4.5V Minimum
3V
V_CC at 3.0V Minimum
Pin States
H
High
L
Low
V
Valid
X
Driven, but not necessarily valid
Z
High Impedance
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