82503 Datasheet, PDF (40/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
RESET TEST AND LOW POWER MODE TIMINGS
Symbol
Parameter
Min Typ Max Units
t₁₈₀
v TEST and JABD Setup Time to RESET
50
t₁₈₁
RESET Pulse Width
300
t₁₈₂
v Low Power Mode Deactivation from TEST and JABD
ns
ns
1
ms
Figure 42 Reset Timings (Test Mode)
290421 – 41
Figure 43 Reset Timings (Start of Low Power Mode)
290421 – 43
Figure 44 Reset Timings (End of Low Power Mode)
290421 – 42
40